1. Field of the Invention
The invention relates to integrated circuits, and more particularly to a bonding pad structure.
2. Description of the Related Art
Bonding pads are interfaces between integrated circuits contained in semiconductor chips and a device package. Modern IC designs with high circuit density require a significantly increased number of pins and bonding pads to reduce bonding pad pitch and size. Large mechanical stresses inherent in bonding operations, however, easily damage smaller bonding pads.
Traditionally, each bonding pad is connected to one or more contact pads on an IC-mounting surface of the device package through wire-bonding, tape automated bonding (TAB) or flip-chip technologies. When an IC chip is probed in an electrical test or the like, a probe pin may damage the soft surface of the bonding pad. The Cu layer beneath the AlCu pad is exposed to air, and may be corroded. The corroded pads caused by this type of pad voids degrade the bondability of wire connection. Currently, a top copper layer of a solid profile is used for connecting an aluminum pad, but has disadvantages of pad voids, narrow bondability window, ball lifting and dielectric crack issues. Accordingly, several modifications of the top copper layer have been developed as listed below. Moreover, in order to overcome this problem, the bonding pad has been divided into a bonding pad region and a sensing pad region, and the probe pin is brought into contact only with the sensing pad region which is allowed to be damaged.
As disclosed in U.S. Pat. No. 6,552,438, one conventional bonding pad comprises a plurality of independent metal plugs formed in an array of via holes of an inter-dielectric layer, in which each metal plug has a bottom portion connected to a lower aluminum layer and a top portion connected to an upper aluminum pad. Moreover, a passivation layer is formed on the aluminum pad to expose a predetermined bonding area for bonding a wire. Another conventional bonding pad comprises a top metal layer filling a lattice trench of an inter-dielectric layer for surrounding dielectric islands. A passivation layer is also formed on the top metal layer to expose a predetermined bonding area for forming an aluminum pad, thus allowing a ball to be bonded on the aluminum pad.
The above-described bonding pads, however, have the following disadvantages. During wafer sorting, wire bonding or probe pin testing, applied forces or large mechanical stresses may crack the inter-dielectric layer adjacent to a probe pin region. Second, the crack may extend into the interior of the inter-dielectric layer surrounding the top metal layer, causing corrosion and layer-open problems. This also causes the aluminum pad to peel from the top metal layer, thus the pad-open problem causes the wire to lose contact with the aluminum pad, decreasing bonding reliability. Additionally, the pitch and size of the bonding pad cannot be further shrinked as the bonding pad is susceptible to damage from the mechanical stress, thus limiting chip size reduction in next generation technologies. Fourth, during wire bonding, a high distribution ratio of the independent metal plugs or the dielectric islands may create a pad finding issue.
As disclosed in U.S. Pat. No. 6,566,752, another conventional bonding pad comprises a top metal ring formed in a trench of an inter-dielectric layer. A passivation layer with a plurality of via holes is formed on the inter-dielectric layer to expose the top metal ring. An aluminum pad is formed on the passivation layer and is electrically connected to the top metal ring through via holes. However, the width of the top metal ring is limited by the via hole design, resulting in a misalignment problem during photolithography, which prohibits bonding pad fabrication within active areas.